Job Description
As the ASIC Physical Design Engineer on our Bitcoin Mining team, you will work closely with other digital designers and mixed signal designers to develop the next generation of mining ASIC in 3nm. In particular, the challenges of block level physical implementation, timing, integration, assembly and physical verification are critical parts of this role.
This role can be based anywhere in the US and Canada. If you prefer an office environment, we have several offices in the U.S. with our hardware labs in Toronto and Oakland.
Qualifications
You Will
- Block level P&R, and integration from early RTL to final tapeout
- Work closely with logic designers on block level timing closure
- Manage interactions with standard cell development and frontend owners
- Improve capacity and scalability of our full chip design flows
- Develop scripts to enhance current physical design infrastructure/methodology
- Collaborate with teammates from different functions and time zones
You Have
- 5+ years of relevant experience with BSEE or Applied Science degree
- Understanding of the full design cycle from RTL to GDSII, including chip level
- Successfully tapped out multiple chips in 5nm and below
- Experience with all aspects of block delivery including clock, power analysis, physical verification, etc.
- Strong Python/Perl/shell/tcl skills
- Experience with Linux and or Unix and text editors
- Understanding of timing constraints and timing reports
- Ability to work effectively in a fast-paced and rapidly changing start-up environment
- Excellent communication skills
Even better if you have experience with
- ICC2 and Fusion Compiler
- Semi-custom implementation and relative placement
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