As a senior ASIC Physical Design Engineer, you will work closely with other digital designers and mixed signal designers to develop the next generation of mining ASIC. In particular, the challenges of block level physical implementation, timing, integration, and physical verification are critical parts of this role.
We are a distributed team across the U.S. and Canada, and are hiring for a single position; we would love to find someone who lives near our lab in Toronto.
Our organization operates as a flat meritocracy, this role’s title is ASIC Physical Design Engineer, but other companies might call this a Technical Lead, Lead Design Engineer, Senior/Staff or Member of Technical Staff role.
You Will:
Perform block level P&R, and integration from early RTL to final tapeout
Work closely with logic designers on block level timing closure
Work closely with custom cell development
Improve capacity and scalability of our full chip design flows
Develop scripts to enhance current physical design infrastructure/methodology
Collaborate with teammates from different functions and time zones
You Have:
10+ years of relevant experience with BSEE or Applied Science degree; 8+ years in combination with a MS degree
Expert in using Synopsys ICC2/Fusion Compiler and PrimeTime
Even better if you have experience with:
CPU/GPU datapath or AI processor physical design
Understanding of the full design cycle from RTL to GDSII, including chip level
Prior experience with custom physical design and relative placement
Successfully tapped out multiple chips in 5nm and below
Experience with all aspects of block delivery including clock, power analysis, physical verification, etc.
Understanding of timing constraints and timing reports
Strong Python/Perl/shell/tcl skills
Experience with Linux and or Unix and text editors
Ability to work effectively in a fast-paced and rapidly changing start-up environment
Excellent communication skills
Even better if you have experience with:
CPU/GPU datapath or AI processor physical design
See more jobs at Square